1. Field of the Invention
The present invention relates to semiconductor storage devices, particular to a DRAM (dynamic random access memory), and a method for manufacturing the same.
2. Description of the Related Art
The memory cell of a DRAM includes a selection transistor and a capacitor. The charge storage of the capacitor is disadvantageously decreasing as the memory cell is miniaturized associating with the progress of microfabrication. In order to overcome this disadvantage, the memory cell has begun to employ a capacitor-over-bitline (COB) structure or a stacked trench capacitor (STC) structure. Specifically, the capacitor is formed over the bitline to increase its base area (projected area) and height, and thus to increase the total area. Typical forms of such capacitors have disclosed in Japanese Unexamined Patent Application Publication Nos. 2002-170940 and 8-316435.
Japanese Unexamined Patent Application Publication No. 2002-170940 has disclosed a COB DRAM cell and a method for manufacturing the COB DRAM cell. The COB DRAM includes a capacitor using a cup-like ruthenium layer as a lower electrode. The ruthenium layer is formed along the internal surface of a hole formed in an insulating interlayer, and has a double-layer structure composed of a first ruthenium sublayer deposited by sputtering and a second ruthenium sublayer deposited by CVD (chemical vapor deposition). However, this patent document does not mention the problem that the shape of the upper end of the lower electrode causes electric field concentration and thus increases the leakage current from the capacitor insulating layer.
Japanese Unexamined Patent Application Publication No. 8-316435 has disclosed a structure using a cup-like polycrystalline silicon layer as the lower electrode. In Japanese Unexamined Patent Application Publication No. 2002-170940, only the internal surface of the cup-like ruthenium layer functions as the lower electrode, while the cup-like polycrystalline silicon layer in Japanese Unexamined Patent Application Publication No. 8-316435 functions as the lower electrode at the internal and external surfaces. In this polycrystalline silicon lower electrode, the upper end is rounded in an addition step to prevent the increase in leakage current resulting from the electric field concentration.
It is considered that such adjustment in the shape of the upper end of the lower electrode reduces the leakage current to some extent.
On the other hand, cost reduction is strongly required in manufacture of DRAM. It is desirable that the upper end of the lower electrode be adjusted without adding a special step as disclosed in Japanese Unexamined Patent Application Publication No. 8-316435. However, the material of the lower electrode (ruthenium, polycrystalline silicon, titanium nitride, etc.) is difficult to form into a desired shape by etching. Furthermore, a photoresist layer and an insulating interlayer are present on the semiconductor substrate when the lower electrode material is etched, and a high etching selectivity of the lower electrode material to those layers must be ensured. It is therefore difficult to adjust the shape of the upper end of the lower electrode.